1. Field of the Invention
The present invention relates to a shared memory controller for controlling a memory shared by a plurality of data groups, to write data into and read data from the shared memory.
2. Description of Related Art
Shared memory schemes are often employed to separately store a plurality of data groups. Here, the term "shared memory scheme" refers to a scheme which is adapted to one or a plurality of physically provided memories to manage addresses of data for each data group to logically organize a plurality of memories. According to this scheme, the memory utilization efficiency can be improved.
The shared memory schemes may be generally classified into two schemes. The first scheme is a so-called linked address scheme which treats a combination of data to be stored and an address indicative of a data storage area for data to be stored next to that data as one unit, and stores this combination into a shared memory. The second scheme writes only data into a shared memory and stores the addresses, at which the data are stored, in an individual fixed-length queue (a fixed memory for addresses) provided separately from the shared memory.
In the following, memory error preventive measures will be described for the scheme which stores addresses in a separate fixed-length queue.
As mentioned above, the shared memory scheme inputs addresses to a memory as well for management. Specifically, as data is input to a shared memory, an address is retrieved from an empty-address memory which stores unused addresses such that the data is written into a storage area of the shared memory indicated by this address, and the address is simultaneously written into an associated queue (FIFO type) within the separate fixed address memory for management. Here, the empty-address memory is previously loaded with addresses available to the shared memory.
The reading of data is performed by reading an address from an address queue associated with the data to be read, and reading data from the shared memory using this address. Simultaneously, the address is written into the fixed empty-address memory. In other words, the shared memory scheme circulates the address values between the empty-address memory and the fixed address memory provided corresponding to a plurality of queues.
Assume herein that an address in an address queue, held in the fixed address memory, is corrupted due, for example, a memory error or the like. In this event, the value of the address will change to another address value, and this corrupted address value circulates between the empty-address memory and the fixed address memory. This causes the same address to be stored in the fixed address memory a plurality of times as an element in different address queues, leading to a further data loss due to any of several reasons such as overwriting of data. In addition, since this phenomenon will recur, appropriate measures should be taken.
Conventionally, certain measures to address the problem mentioned above have been taken in a manner described below. First, each address queue is provided with information indicative of in which address queue an address value is stored, and this information is compared with information when the address is actually read from an associated address queue.
If the comparison shows that the same address value is stored in different address queues, it can be known that the first read address was read from an address queue different from the one indicated by this information. In this event, the address is discarded to make unique the address data having the same address value.
The conventional method of controlling a shared memory mentioned above can be applied to a scheme with separate queues for storing addresses. However, this method cannot be applied to the shared memory scheme (so-called linked address scheme) which stores a combination of an address and data as one unit into a shared memory to achieve a higher memory utilization efficiency.
In the linked address scheme, when data is read, an address indicative of a storage location for the next data is also read. If a memory error occurs in this address value, it is impossible to find a write location for the next data. In this event, addresses stored in an address queue corresponding to the address suffering from the memory error are all lost.
The address queue herein used refers to a queue which is logically organized within the shared memory. While a shorter address queue would lose a smaller amount of addresses even if a memory error occurs therein, more addresses would be lost if a longer address queue suffers from a memory error. In the latter case, a larger storage area would become unavailable, and the memory would fail to function effectively.
Thus, there is a need for a shared memory controller which is capable of maximally preventing a storage area of a shared memory from becoming unavailable even if an address error occurs during a write/read operation.